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A new type of random access memory has been proposed, which will accelerate the development of artificial intelligence
09.02.2021 [11:38],
Gennady Detinich

Solving problems using artificial intelligence is accompanied by the processing of huge amounts of data, which almost always exceed the capabilities of the processor’s cache memory. Therefore, for AI, memory inside the processor and with high energy efficiency will be ideal. This memory was proposed separately from each other by researchers from the United States and Belgium.

Capacitorless memory cell (orange – tungsten-doped indium oxide, yellow – palladium transistor gates, green – nickel drain and source electrodes, blue – hafnium oxide dielectric). Image source: University of Notre Dam

As you know, the classic DRAM RAM is a circuit of one control transistor and a capacitor (1T1C), which stores the charge, then 1 is written in the cell or discharged, which means 0. Energy consumption is spent both for writing data and for reading (when reading, the capacitor loses part of its capacity and it must be replenished), as well as regenerating data in all cells with a frequency of approximately every 64 ms. Researchers from the University of Notre Dame in the USA proposed to solve the problem at the root and presented a DRAM cell without a capacitor, but with two transistors – 2T0C.

The idea is that the gate of a transistor is a small capacitor. Then one transistor in the circuit plays the role of a control transistor (the left one in the diagram below), and the second stores the charge (information). In addition, in the proposed circuit, both transistors operate independently, one of which writes data, and the second reads. For example, if the gate of the second transistor contains a charge, it is open and a current flows through it that can be “read”.

The problem with the implementation of the proposed circuit is exactly one thing – to prevent self-discharge in the gate of the “memory” transistor. Therefore, researchers select semiconductor materials that minimize leakage currents and currents through transistors in the off-state. Regular silicon is not suitable for this. At the University of Notre Dame, for example, a prototype 2T0C cell was made using indium oxide doped to 1% tungsten (IWO). It is argued that the resulting circuit has leakage currents by two to three orders of magnitude less than that of silicon.

Researchers from the Belgian center Imec used other materials in the 2T0C scheme, namely the combination of IGZO (indium, gallium and zinc oxide) already known from Sharp displays. However, for the manufacture of 2T0C memory, the classic technical processes using IGZO did not fit, and they had to be significantly modified. But the memory of Imec turned out to be close to non-volatile. The Belgians had an average retention time of 200 seconds in a 2T0C cell, and 25% of the cells held a charge in excess of 400 seconds, which is thousands of times longer than in the case of conventional DRAM cells. Moreover, Imec expects to be able to bring the data retention time in 2T0C cells without regeneration to 100 hours or more.

Schematic diagram of a memory cell 2T0C. Image source: University of Notre Dam

Finally, 2T0C memory cells, since they do not have capacitors that are rather large in volume, can be made in the working layers of processors or above it. This means that the processor can be endowed with such a large amount of memory that all the data for work can fit in the memory of the processor. Let it not be a cache, but it will still be much closer (and faster in terms of access) to the processor logic than DRAM modules.

All together will be able to raise the execution of AI algorithms to a new and unattainable height today. Ordinary computers can transform too. It remains only to wait for all this.

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